The present invention relates to a semiconductor integrated circuit that can be mounted in an on-vehicle millimeter wave radar device and which incorporates a microprocessor unit (MPU) and an A/D converter, and a method of operating the same and, more particularly, to technology effective when applied to improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter.
In recent years, an on-vehicle millimeter wave radar has attracted attention of each automobile equipment maker as a key part in an adaptive cruise control (ACC) system. The frequency used in an on-vehicle millimeter wave radar is 76 GHz.
Patent Document 1 (Japanese Patent Laid-Open No. 2008-241702), to be described below, describes an on-vehicle radar device comprising a transmission unit to radiate a millimeter wave transmission signal as an electromagnetic wave from a transmitting antenna, a reception unit including a plurality of receiving array antennas to receive a reception signal as a reflected radio wave from a target object, and a target object detection unit to calculate the distance, relative speed, and orientation information of the object from the reception signal of the reception unit. In the reception unit, a plurality of reception signals of the receiving array antennas is amplified by a plurality of RF amplifiers, respectively, and then, down-converted into a plurality of beat signals by a plurality of reception mixers. In the reception unit, the beat signals are further supplied to a plurality of analog input terminals of a plurality of A/D converters via a plurality of low pass filters and a plurality of digital outputs of the A/D converters is accumulated in a buffer unit and output to the target object detection unit.
Patent Document 2 (U.S. Pat. No. 5,486,832 Specification), to be described below, describes a millimeter wave radar system comprising a transmitter including a reference oscillator, a waveform controller, a gun transmitter, etc., and an RF sensor including a plurality of receiving antennas, a plurality of reception mixers, a plurality of low pass filters, and a multiplexer. The multi-input terminal of the multiplexer of the RF sensor is coupled to a plurality of output terminals of the reception mixers via the low pass filters and a plurality of selection control terminals of the multiplexer is controlled by a beam selector and a video signal generated from a radar signal received by the receiving antennas is output sequentially from a single-output terminal of the multiplexer. The output signal of the multiplexer is supplied to a radar signal processor including an amplifier, a video blanking circuit, a single A/D converter, and a range/Doppler processor. The output signal of the range/Doppler processor is supplied to a detection/tracking processor the output signal of which is supplied to a display device.
On the other hand, although not related to the on-vehicle millimeter wave radar directly, Patent Document 3 (Japanese Patent Laid-Open No. 2009-130444) and Patent Document 4 (Japanese Patent Laid-Open No. 2009-159415), to be described below, describe a digital correction type A/D converter capable of high resolution.
The A/D converter described in Patent Document 3 is called a background digital correction type A/D converter and comprises a main A/D conversion unit to execute a high-speed A/D conversion operation with low precision, a reference A/D conversion unit to execute high-resolution A/D conversion at low speed, and a digital correction unit to generate a final digital output signal from the digital signal of the main A/D conversion unit and the digital signal of the reference A/D conversion unit.
The A/D converter described in Patent Document 4 is called a foreground digital correction type A/D converter and comprises a main A/D conversion unit, a reference D/A converter, a switch, a foreground calibration unit, and a digital output generation unit. During the period of calibration operation, the calibration digital signal is converted into a calibration analog signal by the reference D/A converter and the calibration analog signal is supplied to the input of the main A/D conversion unit via the switch. The digital signal of the main A/D conversion unit is supplied to the foreground calibration unit and the digital output generation unit, the calibration digital signal and the final digital output signal of the digital output generation unit are supplied to the foreground calibration unit, and the output of the foreground calibration unit is supplied to the digital output generation unit. As a result of that, the digital output generation unit is controlled by the output of the foreground calibration unit so that the calibration digital signal supplied to the foreground calibration unit and the final digital output signal of the digital output generation unit agree with each other.